In a typical optical media Read/Write channel Integrated Circuit, a wide range of clock frequencies are often needed to accommodate different data rates and different optical storage media. Even when using a single media, a multiple speed operation often needs to be supported. The channel bit data rates of a 1×DVD, a 1×CD and a 1× blu-ray disc (BD) are 26.16 Mbps, 4.32 Mbps and 66 Mbps, respectively. A DVD R/W channel can operate at speeds ranging from 1˜16×. A 16×DVD operation has a transfer rate of up to 418.56 Mbps. A CD R/W channel operates at speeds from 1˜52×. A 56×CD operation can reach a transfer rate of up to 224.64 Mbps. A wide frequency range in clock generation is necessary to support such a wide range of bit rates.
In conventional approaches, in order to cover a wide frequency range, a Voltage Controlled Oscillator (VCO) using a single large Kvco (i.e., a gain value of the VCO) has been implemented. For example, see (I. A. Young, J. K. Greason, K. L. Wong, “A PLL Clock Generator with 5 to 110 Mhz of Lock Range for Microprocessors,” IEEE J. Solid-State Circuits, pp. 1599-1607, November 1992. Also see John G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE J. Solid-State Circuits, pp. 1723-1732, November 1996.). However, a large Kvco causes more sensitivity to noise on the output node of the charge pump. Also, it is practically impossible to keep a certain constant ratio ωn/ωc for all frequencies using conventional approaches. It is important to meet the timing loop bandwidth ωn to an oscillator frequency ωc relationship for a data acquisition and tracking for DVD read channel system. Using such conventional techniques, in order to achieve a wide oscillation frequency range, the amplitude control loop (ACL) loop bandwidth variation caused by a VCR (Voltage Controlled Resistor) stage needs to be compensated.
In certain system designs, if the ICO oscillation frequency becomes higher, a fast response at the ICO is also needed. In such a system, the ACL loop bandwidth needs to be increased as the oscillation frequency goes higher. Another problem with conventional approaches occurs. When the oscillation frequency becomes slow, a control current then becomes lower. This increases the gain of the VCR, so the bandwidth of the ACL becomes larger. This frequency becomes a 2nd pole of the PLL. As the bandwidth of the amplitude control loop increases and approaches the bandwidth of the PLL, the oscillator becomes unstable.
Due to weak gain characteristics of a conventional MOS transistor, it is not practical, or even possible, to maintain a fixed ring oscillator swing voltage for a wide frequency range with the diode characteristics of a MOS transistor. For a wide frequency oscillation range, the ACL (amplitude controlled loop) is adopted to keep a targeted amplitude swing voltage in an oscillator.
It would be desirable to implement an oscillation design that resolves the problem with opposite direction amplitude control loop bandwidth in an oscillator.